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[VHDL-FPGA-Verilog] FIFO

Description: fifo异步串口收发程序 FPGA程序-fifo asynchronous serial transceiver
Platform: | Size: 2203648 | Author: 张哲 | Hits:

[USB develop] SLAVE-FIFO-16BITS

Description: CY7C68013a的slavefifo的固件源代码，keil编写，以及使用FPGA向EP6端点写数据的verilog源代码，没有错误，可以编译成功!-CY7C68013a of slavefifo firmware source code, keil prepared using FPGA and write data to the endpoint EP6 verilog source code, no errors, you can compile successfully!
Platform: | Size: 223232 | Author: 向新铭 | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 先入先出FIFO，实现缓存功能，异步的还实现转换频率的功能，在FPGA里十分常用。-FIFO,First input,First output
Platform: | Size: 3256320 | Author: 敏洁 | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 基于FPGA的fifo例程及仿真测试文件。-Fifo FPGA-based emulation routines and test files.
Platform: | Size: 10864640 | Author: 金慧宇 | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 先进先出模块，该模块可以用来调节数据的速率，而且可以作为暂时存储器使用，一般的FPGA调试时使用较多。-frist in frist out
Platform: | Size: 1024 | Author: yanh | Hits:

[Program doc] FIFO

Description: 一本详细介绍了FPGA编程中常用的FIFO模块的使用方法以及详细解释，外国大牛写的，很有参考意义。-A detailed introduces the method of using FIFO module used in FPGA programming and explain in detail, foreign Daniel wrote, of great reference significance.
Platform: | Size: 562176 | Author: 阳松 | Hits:

[ARM-PowerPC-ColdFire-MIPS] FPGA

Description: 实现USB的slave FIFO功能的FPGA部分-Implementation of USB slave FIFO
Platform: | Size: 84992 | Author: hugd | Hits:

[VHDL-FPGA-Verilog] fifo

Description: CAN总线，DSP+FPGA+SJA1000架构，FPGA负责逻辑设计,此文件内有FPGA负责dsp和sja1000通信-CAN bus, DSP+ FPGA+ SJA1000 architecture, FPGA logic is responsible for the design, FPGA is responsible in this document have dsp and sja1000 Communications
Platform: | Size: 4096 | Author: 张浩阳 | Hits:

[File Format] Altera-FIFO

Description: 介绍了Altera的FPGA的FIFO的功能与介绍-Introduction of Altera' s FPGA capabilities with the introduction of the FIFO
Platform: | Size: 701440 | Author: 王兵兵 | Hits:

[VHDL-FPGA-Verilog] FPGA-Source-Code_VHDL

Description: cypress fx2lp slave fifo fpga控制端源码-source code of FX2LP_SLAVE_FIFO CONTROLLER S
Platform: | Size: 1172480 | Author: 赵 | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 同步时钟FIFO已经在FPGA及modelsim中充分验证-Synchronous FIFO has been fully validated
Platform: | Size: 135168 | Author: seer | Hits:

[VHDL-FPGA-Verilog] uart

Description: 带有fifo的功能模块，具有发送模块和接收功能模块(The function module with FIFO has transmitting module and receiving function module)
Platform: | Size: 145408 | Author: 陈陈陈啊 | Hits:

[VHDL-FPGA-Verilog] uartverilog

Description: FPGA利用串口、FIFO实现串口收发数据(FPGA using serial port, FIFO serial transceiver data)
Platform: | Size: 196608 | Author: mzl127 | Hits:

[VHDL-FPGA-Verilog] CCD_Array

Description: Interface TCD1209DG with Altera FPGA and transfer image data to PC via USB using USB FX2 Slave FIFO mode, Only FPGA code included.
Platform: | Size: 3320832 | Author: muralidh | Hits:

[VHDL-FPGA-Verilog] parameter_uart_rx

Description: 串口接收模块，可以通过parameter，参数化配置传输速率、传输位宽和校验。采用Verilog语音编程实现。使用者根据串口的要求配置好参数，并根据缓冲的大小配置FIFO就可以使用。对帧错误（停止位不为高），检验错误和读FIFO超时（FIFO满的情况下，有新的数据到）等现象进行了检查。(UART serial receiver module, through parameter, configuration parameters of the transmission rate, Data width and parity. Using Verilog. The user configured the parameters according to the serial port and configured FIFO according to the size of the buffer. The frame error (stop bit is not high), check errors, and read FIFO timeout (when FIFO is full,and new data come) and so on are examined.)
Platform: | Size: 4096 | Author: 老工程师 | Hits:

[VHDL-FPGA-Verilog] syn_dp_fifo.v

Description: 同步双端口FIFO, 可同时读写，FIFO深度宽度可通过参数配置，带SV断言测试。(Dual Port Synchronization FIFO for ASIC/FPGA)
Platform: | Size: 1024 | Author: junkaizhan | Hits:

[VHDL-FPGA-Verilog] sp6ex19

Description: FPGA片内FIFO实例，对FPGA片内FIFO进行读写测试(FPGA examples of FIFO, FPGA on-chip FIFO reading and writing test)
Platform: | Size: 5181440 | Author: 没伞的孩子 | Hits:

[VHDL-FPGA-Verilog] SDRAM缓冲测试程序

Description: 对FPGA的SDRAM进行测试，主要是实现FIFO-SDRAM-FIFO的数据传输(Test the SDRAM of the FPGA)
Platform: | Size: 76057600 | Author: 降落 | Hits:

[VHDL-FPGA-Verilog] 20170808_fifo_xc5v_v1.5

Description: FPGA通过fifo进行数据的载入载出，实现数据的暂时存储和传递(FPGA through fifo data loading and unloading, to achieve temporary storage and delivery of data)
Platform: | Size: 10388480 | Author: bingbinglong | Hits:

[VHDL-FPGA-Verilog] eetop.cn_FIFO_Buffer

Description: 异步FIFO的Verilog程序及其测试程序(FPGA/Verilog FIFO_ASYN)
Platform: | Size: 68608 | Author: 半岛铁盒 | Hits:
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